Table of Contents
Advertisement
CHAPTER 23 CAN CONTROLLER
23.6.17
Reception Interrupt Enable Register (RIER)
Reception interrupt enable register (RIER) enables or disables the reception interrupt by
the message buffer (x).
The reception interrupt is generated at reception completion (when RCx of the reception
completion register (RCR) is "1").
■ Reception Interrupt Enable Register (RIER)
Figure 23.6-20 Configuration of the Reception Interrupt Enable Register (RIER)
Address:
CAN0: 00007F
CAN1: 0000BF
CAN2: 00357F
CAN3: 00358F
CAN4: 00359F
Address:
CAN0: 00007E
CAN1: 0000BE
CAN2: 00357E
CAN3: 00358E
CAN4: 00359E
[bit15 to bit0] RIE15 to RIE0:
"0": Reception interrupt disabled.
"1": Reception interrupt enabled.
490
bit
15
14
13
12
11
H
RIE15 RIE14 RIE13 RIE12 RIE11 RIE10 RIE9 RIE8
H
H
R/W R/W R/W R/W
R/W
H
H
bit
7
6
5
4
3
H
RIE7 RIE6 RIE5 RIE4 RIE3 RIE2 RIE1 RIE0
H
H
R/W R/W R/W R/W
R/W
H
H
10
9
8
RIERn (upper)
Initial value
0 0 0 0 0 0 0 0
R/W
R/W R/W
2
1
0
RIERn (lower)
Initial value
0 0 0 0 0 0 0 0
R/W
R/W R/W
B
B
n = 0, 1, 2, 3, 4
Advertisement
Table of Contents
