Uart0, Uart1 Block Diagram - Fujitsu MB90390 Series Hardware Manual

19.2

UART0, UART1 Block Diagram

Figure 19.2-1 shows the UART0, UART1 block diagram.
■ UART0, UART1 Block Diagram
CONTROL BUS
Dedicated baud rate clock
16-bit reload timer 0
SCK0
SIN0
UMC
register
Figure 19.2-1 UART0, UART1 Block Diagram
Receive clock
Clock select
circuit
Receive status
evaluation circuit
Receive error
indication signal
2
for EI OS (to CPU)
PEN
SBL
MC1
USR
MC0
register
SMDE
RFC
SCKE
SOE
T r ansmit clock
Receive control circuit
Start bit detect
circuit
Receive bit counter
Receive parity
counter
Receive shifter
Receive
complete
UIDR
Data bus
RDRF
ORFE
PE
URD
TDRE
register
RIE
TIE
RBF
TBF
Note: this diagram is valid for UART0, UART1
CHAPTER 19 UART0, UART1
Receive interrupt
(to CPU)
SCK0
T r ansmit interrupt
(to CPU)
T r ansmit control circuit
T r ansmit start circuit
T r ansmit bit counter
T r ansmit parity
counter
SOT0
T r ansmit shifter
T r ansmit start
UODR
BCH
RC3
RC2
RC1
RC0
BCH0
P
D8
CONTROL BUS
313