Fujitsu MB90390 Series Hardware Manual page 227

Table 13.3-1 Control Status Register of Free-run Timer (Lower)
Bit name
IVF:
bit7 Interrupt request flag
bit and clear bit
IVFE:
bit6
STOP:
bit5
STOP bit
MODE:
bit4
MODE bit
CLR:
bit3
CLR bit
bit2 to CLK2, CLK1,
bit0 CLK0:
• This bit is the interrupt request flag bit and clear bit
• Writing "0": A possible interrupt is cleared.
• Writing "1": No effect.
• "1" is always read during a read-modify-write (RMW) instructions cycle.
• This bit enables the interrupt request
• Writing "0": Interrupt disabled.
• Writing "1": Interrupt enabled.
• The STOP bit is used to stop the timer.
• Writing "0": Counter enabled (operation).
• Writing "1": Counter disabled (stop).
• "0": Initialization by reset or clear bit
• "1": Free-run timer 0: Initialization by reset, clear bit, or compare register 0
Free-run timer 1: Initialization by reset, clear bit, or compare register 4
• The CLR bit initializes the operating free-run timer to the value "0000
• Writing "0": no effect.
• Writing "1": Counter is initialized.
Note:
To initialize the counter value while the timer is stopped, write "0000
register.
These bits are used to select the count clock for the 16-bit-free-run timer. The clock is
updated immediately after a value is written to these bits. Therefore, ensure that the
input capture operations are stopped before a value is written to these bits.
CLK2 CLK1 CLK0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
CHAPTER 13 16-BIT I/O TIMER
Function
φ = φ =
Count
clock
20 MHz 16 MHz
φ
50 ns 62.5 ns
φ / 2
100 ns 125 ns
φ / 4 0.2 μs 0.25 μs
φ / 8 0.4 μs 0.5 μs
φ / 16 0.8 μs 1 μs
φ / 32 1.6 μs 2 μs
φ / 64 3.2 μs 4 μs
φ / 128 6.4 μs 8 μs
"
B
" to the data
B
φ = φ = φ =
8 MHz 4 MHz 1 MHz
0.25 μs 1 μs
125 ns
0.25 μs 0.5 μs 2 μs
0.5 μs 1 μs 4 μs
1 μs 2 μs 8 μs
2 μs 4 μs 16 μs
4 μs 8 μs 32 μs
8 μs 16 μs 64 μs
16 μs 32 μs 128 μs
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