Output Of The Main Clock Hclk And Hclkx - Fujitsu MB90390 Series Hardware Manual

5.7

Output of the main clock HCLK and HCLKX

For the control of output of the main clock HCLK and HCLKX, the clock output Enable
Register is used.
■ Clock Output Enable Register
bit
Address:
0 0 0 0 3 F
H
: Oscillation clock
HCLK
HCLKX : Inverted Oscillation clock
: Readable and writable
R/W
: Undefined value
X
-
: Undefined
: Initial value
Table 5.7-1 Function of Each Bit of the Clock Output Enable Register
bit15 to
bit10
bit9
bit8
Figure 5.7-1 Clock Output Enable Register (CKOE)
15 14 13 12 11
- - -
-
- - - -
Bit name
Undefined
If this bit is set to "1" the HCLKX output on pin 92 (P97) is enabled. If it is
CKXOE
set to "0" the HCLKX output is disabled
If this bit is set to "1" the HCLK output on pin 91 (PB7) is enabled.
CKOE
If it is set to "0" the HCLK output is disabled
10 9 8
CKXOE CKOE
-
-
-
- R/W R/W
HCLK output enable
CKOE
0 HCLK output is disabled
1 HCLK output is enabled
CKXOE HCLKX output enable
HCLKX output is disabled
0
HCLKX output is enabled
1
CHAPTER 5 CLOCKS
Initial value
X X X X X X 0 0
Function
-
B
103