Fujitsu MB90390 Series Hardware Manual page 214

CHAPTER 12 WATCHDOG TIMER
[bit1, bit0] WT1, WT0
These bits are used to select the watchdog timer interval. Only the data items written during watchdog
timer activation are valid. Data items that are written outside watchdog timer activation are ignored.
Table 12.1-2 lists the interval settings.
These bits are write only bits.
Table 12.1-2 Watchdog Timer Interval Selection Bit
WT1
0
0
1
1
*: For a source oscillation of 4 MHz.
Note:
The interval time uses the carry signal of the time-base timer or clock timer as a count clock. If the
time-base timer or clock timer is cleared, the interval time of the watchdog timer may become long.
The time-base timer is also cleared by writing "0" to the TBR bit in the time-base timer control
register (TBTC), transition from main clock mode to PLL clock mode.
186
WT0
Minimum
0 approx. 3.58 ms
1 approx. 14.33 ms
0 approx. 57.23 ms
1 approx. 458.7 ms
Interval *
Maximum
approx. 4.61 ms
approx. 18.43 ms
approx. 73.73 ms
approx. 589.82 ms
Main clock cycle count
14 11
2 plus or minus 2
cycles
16 13
2 plus or minus 2
cycles
18 15
2 plus or minus 2
cycles
21 18
2 plus or minus 2
cycles