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CHAPTER 16 8/16-BIT PPG
Table 16.3-1 Bit Function Description of the PPG0 Operation Mode Control Register
Bit name
PEN0:
bit7
Operation enable bit
PE00:
bit5
PPG00 pin output
enable bit
PIE0:
bit4
PPG interrupt enable
bit
PUF0:
bit3
PPG counter
underflow bit
bit0
Reserved bit.
256
When set to "1", this bit enables the counter operation of the PPG. When operation is
disabled but output is enabled (bit5), a "L" level is maintained at the output.
When set to "1", this bit enables the pulse output. For MB90390 Series, the pulse signal is
output to the "PPG00" external pin. When disabled, the pin can be used as general-
purpose port.
While this bit is "1", an interrupt request is issued as soon as PUF0 is set to "1". No
interrupt request is issued while this bit is set to "0".
In 8-bit PPG 2-channel mode or 8-bit prescaler + 8-bit PPG mode, this bit is set to "1"
when an underflow occurs as a result of the ch.0 counter value becoming from "00
"FF
". In 16-bit PPG mode, this bit is set to "1" when an underflow occurs as a result of
H
the Channel 0 and 1 counter value changing from "0000
"0", write "0". Writing "1" to this bit has not effect. Upon a read operation during a read-
modify-write (RMW) instruction, "1" is read.
This is a reserved bit. When setting PPGC0, always set this bit to "1".
Function
" to "FFFF
H
" to
H
". To set this bit to
H
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