Bit Timing Register (Btr) - Fujitsu MB90390 Series Hardware Manual

23.6.5

Bit Timing Register (BTR)

Bit timing register (BTR) stores the prescaler and bit timing setting.
■ Bit Timing Register (BTR)
R/W : Readable and writable
Note:
This register should be set during bus operation stop (HALT = 1).
■ Bit Timing Register (BTR) Contents
Table 23.6-6 Function of Each Bit of the Bit Timing Register (BTR)
Bit name
bit15 Undefined
TS2.2 to TS2.0:
bit14 to
Time segment2
bit12
setting bits
TS1.3 to TS1.0:
bit11 to
Time segment1
bit8
setting bits
RSJ1, RSJ0:
Resynchronization
bit7, bit6
jump width setting
bits
PSC5 to PSC0:
bit5 to bit0 Prescaler setting
bits
Figure 23.6-6 Configuration of the Bit Timing Register (BTR)
Address:
bit 15 14
CAN0: 003707
H
- TS2.2 TS2.1 TS2.0 TS1.3 TS1.2 TS1.1 TS1.0
CAN1: 003907
H
CAN2: 003B07
H
- R/W R/W R/W
CAN3: 003D07
H
CAN4: 003F07
H
Address:
bit 7 6
CAN0: 003706
H
RSJ1 RSJ0 PSC5 PSC4 PSC3 REC2 PSC1 PSC0
CAN1: 003906
H
CAN2: 003B06
H
R/W R/W R/W R/W
CAN3: 003D06
H
CAN4: 003F06
H
These bits define the number of the time quanta (TQ's) for the time segment 2 (TSEG2).
The time segment 2 is equal to the phase buffer segment 2 (PHASE_SEG2) in the CAN
specification.
These bits define the number of the time quanta (TQ's) for the time segment 1 (TSEG1).
The time segment 1 is equal to the propagation segment (PROP_SEG) + phase buffer
segment 1 (PHASE_SEG1) in the CAN specification.
These bits define the number of the time quanta (TQ's) for the resynchronization jump
width.
These bits define the time quanta (TQ) of the CAN controller. (see below for details.)
13 12 11 10 9 8
R/W R/W R/W R/W
5 4 3 2 1 0
R/W R/W R/W R/W
Function
CHAPTER 23 CAN CONTROLLER
BTR (upper)
Initial value
X 1 1 1 1 1 1 1
B
BTR (lower)
Initial value
1 1 1 1 1 1 1 1
B
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