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Machine clock
Reload
Counter
SCK2/SCK3
Pin
SIN2/SIN3
Pin
Over -
sampling
Unit
LIN break
Signal
and Synch
to ICU
Field
Detection
circuit
2
To EI
OS
PE
ORE
SSR2/
FRE
SSR3
RDRF
register
TDRE
BDS
RIE
TIE
Figure 20.2-1 Block Diagram of UART2, UART3
(OTO,
EXT,
REST)
transmission clock
reception clock
RECEPTION
CONTROL
CIRCUIT
Start bit
Detection
circuit
Restart Reception
Reload Counter
Received
Bit counter
Received
Parity counter
Reception
shift register
Err or
Detection
RDR2/RDR3
PE
ORE
FRE
Internal data bu s
PEN
MD1
P
MD0
SMR2/
SBL
OTO
SMR3
EXT
CL
register
REST
A/D
UPCL
CRE
RXE
SCKE
SOE
TXE
TRANSMISSION
CONTROL
CIRCUIT
Transmission
Start circuit
Transmission
Bit counter
Transmission
Parity counter
reception
complete
SIN3
Transmission
shift register
TDR2/TDR3
LBD
LBIE
LBD
ESCR2/
SCR2/
LBL1
ESCR3
SCR3
LBL0
register
register
SOPE
SIOP
CCO
SCES
CHAPTER 20 UART2, UART3
PE
ORE
FRE
TIE
RIE
LBIE
Interrupt
LBD
Generation
circuit
RBI
TBI
reception
IRQ
transmission
TDRE
IRQ
SOT2/3
Pin
RDRF
SOT3
SIN3
LIN
break
genera-
tion
transmission
circuit
start
Bus idle
Detection
circuit
RBI
TBI
LBR
ECCR2/
MS
ECCR3
SCDE
register
SSM
RBI
TBI
LBR
LBL1
LBL0
343
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