Fujitsu MB90390 Series Hardware Manual page 245

■ Control Status Register
Address:
bit 15/7
000054
H
000055
H
000056
R/W R/W R/W R/W R/W
H
R/W : Readable and writable
: Initial value
Figure 13.5-3 Control Status Register (ICS)
14/6 13/5 12/4 11/3 10/2 9/1 8/0
R/W R/W R/W
ICS01
Initial value
ICS23
0 0 0 0 0 0 0 0
B
ICS45
bit9/bit1 bit8/bit0
EGn1 EGn0 Edge selection bit (input capture n)
0 0 No edge detection (stop)
0 1 Rising edge detection
1 0 Falling edge detection
1 1 Both edges detection
bit11/bit3 bit10/bit2
EGm1 EGm0 Edge selection bit (input capture m)
0 0 No edge detection (stop)
0 1 Rising edge detection
1 0 Falling edge detection
1 1 Both edges detection
bit12/bit4
Interrupt Enable Bit (input capture n)
ICEn
0 Disable Interrupt
1 Enable Interrupt
bit13/bit5
Interrupt Enable Bit (input capture m)
ICEm
0 Disable Interrupt
1 Enable Interrupt
bit14/bit6
Interrupt request flag bit (input capture n)
ICPn
Read
0 No valid detected
1 Valid detected
bit15/bit7
Interrupt request flag bit (input capture m)
ICPm
Read
0 No valid detected
1 Valid detected
CHAPTER 13 16-BIT I/O TIMER
Write
Clear this bit
No effect
Write
Clear this bit
No effect
n = 0, 2, 4 m = 1, 3, 5
217