Table of Contents
Advertisement
CHAPTER 23 CAN CONTROLLER
Figure 23.6-23 Configuration of the Acceptance Mask Register 1 (AMR1)
Address:
CAN0: 003718
CAN1: 003918
CAN2: 003B18
CAN3: 003D18
CAN4: 003F18
Address:
CAN0: 003719
CAN1: 003919
CAN2: 003B19
CAN3: 003D19
CAN4: 003F19
Address:
CAN0: 00371A
CAN1: 00391A
CAN2: 003B1A
CAN3: 003D1A
CAN4: 003F1A
Address:
CAN0: 00371B
CAN1: 00391B
CAN2: 003B1B
CAN3: 003D1B
CAN4: 003F1B
R/W
:
Readable and writable
X
:
Undefined value
-
:
Undefined
●
0: Compare
Compare the bit of the acceptance code (ID register IDRx for comparing with the received message ID)
corresponding to this bit with the bit of the received message ID. If there is no match, no message is
received.
●
1: Mask
Mask the bit of the acceptance code ID register (IDRx) corresponding to this bit. No comparison is made
with the bit of the received message ID.
Notes:
• AMR0 and AMR1 should be set when all the message buffers (x) selecting AMR0 and AMR1 are
invalid (BVALx of the message buffer valid register (BVALR) is "0"). Setting when the buffers are
valid (BVALx = 1) may cause unnecessary received messages to be stored.
• To invalidate the message buffer (by setting the BVALR: BVAL bit to "0") while the CAN controller
is operating for CAN communication (the read value of the CSR: HALT bit is "0" and the CAN
controller is operating for CAN bus communication to enable transmission and reception), follow
the procedure in Section "23.16 Precautions when Using CAN Controller".
494
bit
7
6
5
4
3
H
AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21
H
H
R/W R/W R/W R/W
R/W
H
H
bit
15
14
13
12
11
H
AM20 AM19 AM18
AM17 AM16 AM15 AM14 AM13
H
H
R/W R/W R/W R/W
R/W
H
H
bit
7
6
5
4
3
H
AM12 AM11 AM10 AM9 AM8 AM7 AM6 AM5
H
H
R/W R/W R/W R/W
R/W
H
H
15
14
13
12
11
bit
H
AM4 AM3 AM2 AM1 AM0
H
H
R/W R/W R/W R/W
R/W
H
H
2
1
0
AMR1n Byte 0
Initial value
X X X X X X X X
R/W
R/W R/W
10
9
8
AMR1n Byte 1
Initial value
X X X X X X X X
R/W
R/W R/W
2
1
0
AMR1n Byte 2
Initial value
X X X X X X X X
R/W
R/W R/W
10
9
8
AMR1n Byte 3
-
-
-
Initial value
X X X X X X X X
-
-
-
n = 0, 1, 2, 3, 4
B
B
B
B
Advertisement
Table of Contents
