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CHAPTER 5 CLOCKS
5.3.1
Clock Selection Register (CKSCR)
The clock selection register (CKSCR) is used to switch between the main clock and a
PLL clock and is also used to select an oscillation stabilization wait time and a PLL
clock multiplier.
■ Configuration of the Clock Selection Register (CKSCR)
Figure 5.3-2 shows the configuration of the clock selection register (CKSCR). Table 5.3-1 describes the
function of each bit of the clock selection register (CKSCR).
Figure 5.3-2 Configuration of the Clock Selection Register (CKSCR)
bit
Address:
0 0 0 0 A 1
H
: Oscillation clock
HCLK
: Readable and writable
R/W
: Read only
R
: Initial value
Note:
The machine clock selection bit is initialized to main clock selection at a reset.
92
15
14
13
12
11
MCM WS1
WS0
Reserved
Reserved
R/W
R
R/W
R/W
R/W
10
9
8
CS0
(LPMCR)
MCS
CS1
R/W
R/W
R/W
CS2
CS1
CS0
The resulting clock for 4 and 5 MHz crystal
0
0
1 x HCLK (4MHz / 5 MHz)*
0
0
0
1
2 x HCLK (8MHz / 10 MHz)*
1
0
3 x HCLK (12MHz / 15 MHz)*
0
1
1
4 x HCLK (16MHz / 20 MHz)*
0
1
0
0
2 x HCLK (8MHz / 10 MHz)
1
0
1
4 x HCLK (16MHz / 20 MHz)
1
0
6 x HCLK (24MHz / Set up Prohibition)
1
1
1
Prohibition
1
*: The setting exceeded 20MHz is disabled.
Machine clock selection bit
MCS
0
PLL clock selected.
1
Main clock selected.
Oscillation stabilization wait time selection bits
WS1 WS0
The corresponding time interval for an oscillation clock
of 4 MHz / 5 MHz is given in parentheses.
10
/ HCLK(Approx. 256/204.8 μs)
0
0
2
13
2
/ HCLK (Aprox. 2.05/1.64
0
1
15
1
0
2
/ HCLK (Aprox. 8.19/6.55
1
7
1
1
2
/ HCLK (Aprox. 32.77/26.22
MCM
MCM
Machine clock indication bit
Running on a PLL clock.
0
Running on the main clock.
1
* If a power-on reset occurs the oscillation stabilization
18
ait time is 2
/HCLK (approx. 65.54 ms).
0
Initial value
1 1 1 1 1 1 0 0
B
CS2(PLLC register:bit8)
Multiplier selection bits
is given in parentheses.
ms)
ms)
ms)*
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