Fujitsu MB90390 Series Hardware Manual page 240

CHAPTER 13 16-BIT I/O TIMER
■ Sample Output Waveform when CMOD[1:0] = 10
The operation mode defined by CMOD[1:0] = 10
signals for each free-run timer instead of two. If this mode is set to OCU module 1, a match of the timer
value with compare register 0 reverses both OUT2 and OUT3. For the third pulsed signal, the
CMOD[1:0] bits of OCU module 0 should be set to "01
In register OCS1: CMOD[1:0] = 01
OUT0: The level is only reversed by a match with compare register 0.
OUT1: The level is reversed by a match with compare register 0 or with compare register 1.
In register OCS3: CMOD[1:0] = 10
OUT2: The level is reversed by a match with compare register 0 or with compare register 2.
OUT3: The level is reversed by a match with compare register 0 or with compare register 3.
For OUT4, OUT5, OUT6 and OUT7, compare register 4 plays the same role as compare register 0 above.
Figure 13.4-9 Output Waveform when OCS1:CMOD[1:0] = 01
Counter value
FFFF
H
BFFF
H
7FFF
H
3FFF
H
0000
H
Reset
OCCP0 value
OCCP1 value
OCCP2 value
OCCP3 value
OUT0
OUT1
OUT2
OUT3
Note: In this figure, the initial value is "0" for all pins. Timer reset is by match with compare register 0.
212
B
is intended for the use of three pulse width modulated
B
".
B
B
B
BFFF
H
7FFF
H
3FFF
H
5FFF
H
and OCS3:CMOD[1:0] = 10
B B
Time