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CHAPTER 8 LOW-POWER CONTROL CIRCUIT
■ Priorities of the STP, SLP, and TMD Bits
If the stop mode, sleep mode, and time-base timer mode are requested concurrently, the stop mode request,
time-base timer mode request, and sleep mode request are given priorities in this order for processing.
Note:
To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop
mode or time-base timer mode, disable the output of peripheral functions, and set the STP bit of the
low-power consumption mode control register (LPMCR) to "1" or set the TMD bit to "0".
This applies to the following pins:
P03/IN3/OUT6, P05/IN5/OUT7, P06/OUT0, P07/OUT1, P10/OUT2, P11/OUT3, P12/OUT4,
P13/OUT5, P15/TOT0, P16/SGO, P17/SGA, P20/TX1, P31/TX0, P33/TOT1, P34/SOT0, P35/SCK0
Table 8.3-2 Instructions to be Used for Switching to a Low-power Consumption Mode
MOV io,#imm8
MOV io,A
MOV @RLi+disp8,A
MOVW io,#imm16
MOVW io,A
MOVW @RLi+disp8,A
SETB io:bp
CLRB io:bp
146
MOV dir,#imm8
MOV dir,A
MOVW dir,#imm16
MOVW dir,A
SETB dir:bp
CLRB dir:bp
MOV eam,#imm8
MOV addr16,A
MOVW eam,#imm16
MOVW addr16,A
SETB addr16:bp
CLRB addr16:bp
MOV eam,Ri
MOV eam,A
MOVW eam,RWi
MOVW eam,A
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