Block Diagram Of Can Controller - Fujitsu MB90390 Series Hardware Manual

23.2

Block Diagram of CAN Controller

Figure 23.2-1 shows a block diagram of the CAN controller.
■ Block Diagram of CAN Controller
2
F MC-16LX bus
Clock
PSC
TS1
BTR
TS2
RSJ
TOE
TS
RS
CSR
HALT
NIE
NT
NS1,NS0
RTEC
BVALR
TREQR
TCANR
TRTRR
RFWTR
TCR
TIER
RCR
RIER
RRTRR
ROVRR
AMSR
AMR0
AMR1
IDR0 to IDR15
DLCR0 to DLCR15
DTR0 to DTR15
RAM
LEIR
LDER
Figure 23.2-1 Block Diagram of CAN Controller
Prescaler
Bit timing generation
1 to 64 frequency division
Node status change Node status
interrupt generation change interrupt
TBFx, clear
T r ansmitting
TBFx
buffer x decision
TBFx
TBFx, set, clear
T r ansmission
T r ansmission complete
complete
interrupt generation
interrupt
RBFx, set
Reception
Reception complete
complete
interrupt generation
interrupt
RBFx, TBFx, set, clear
IDSEL
RBFx, set
0
1
Acceptance Receiving buffer x
filter decision
RBFx
RAM address
RBFx, TBFx, RDLC, TDLC, IDSEL
generation
TQ (Operating clock)
SYNC, TSEG1, TSEG2
Bus state
machine
Error
control
T r ansmitting/receiving
sequencer
Data Acceptance
counter filter control
TDLC RDLC IDSEL
BITER, STFER,
ARBLOST
CRCER, FRMER,
ACKER
T r ansmission
shift register
CRC
generation
TDLC
CRCER
RDLC
CRC generation/error
check
Receive shift Destuffing/stuffing
register
ARBLOST
BITER
ACKER
FRMER
CHAPTER 23 CAN CONTROLLER
IDLE, INT , SUSPND,
transmit, receive,
ERR, OVRLD
Error frame
generation
Overload
frame
generation
Output
driver
Stuffing
ACK
generation
STFER
error check
Arbitration
check
Bit error
check
PH1
Acknowledgment
error check
Form error Input
check latch
TX
RX
457