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For -H Devices,e.q. MB90F394H and MB90V390H:
Caution for Disabling Message Buffers by
BVAL Bits ......................................... 519
Pin Assignment of MB90V390H ........................... 9
MB90V390HA
Pin Assignment of
MB90V390HA/MB90V390HB .............. 10
MB90V390HB
Pin Assignment of
MB90V390HA/MB90V390HB .............. 10
Memory Access Modes
Memory Access Modes..................................... 164
Memory Space
Memory Space Map ........................................... 30
Multi-byte Data Allocation in Memory Space ....... 35
Outline of CPU Memory Space ........................... 27
Message Buffer
For Non-H Devices,e.q. MB90V390: Caution for
Disabling Message Buffers by BVAL
Bits .................................................... 520
List of Message Buffers (DLC Registers and Data
Registers) ........................................... 463
List of Message Buffers (ID Registers)............... 460
Message Buffers....................................... 466, 495
Procedure for Reception by Message Buffer
(x)...................................................... 512
Procedure for Transmission by Message
Buffer (x) ........................................... 510
Setting Configuration of Multi-level Message
Buffer ................................................ 514
Message Buffer Control Registers
Message Buffer Control Registers...................... 466
Message Buffer Valid Register
Message Buffer Valid Register (BVALR)........... 479
Minimum Connection
Example of Minimum Connection to the Flash
Microcontroller Programmer (Power
Supplied From the Programmer) ........... 602
Example of Minimum Connection to the Flash
Microcontroller Programmer (User Power
Supply Used) ...................................... 600
Mode Data
Mode Data....................................................... 166
Status of Pins after Mode Data is Read ............... 136
Mode Fetch
Mode Fetch...................................................... 132
Mode Pins
Mode Pins ............................................... 131, 165
Modulation Degree
Modulation Degree and Frequency Resolution in
Frequency Modulation Mode................ 106
Modulation Parameter
Modulation Parameter for Frequency Modulation
Mode ................................................. 122
704
Modulation Parameter Register
Modulation Parameter Register ......................... 114
Modulation Parameter Register Contents............ 115
Multi-byte Data
Accessing Multi-byte Data.................................. 35
Multi-byte Data Allocation
Multi-byte Data Allocation in Memory Space....... 35
Multi-level Message Buffer
Setting Configuration of Multi-level Message
Buffer ................................................ 514
Multiple Interrupts
Multiple Interrupts ............................................. 68
Multiplier
Selection of a PLL Clock Multiplier .................... 97
N
NCC
Flag Change Disable Prefix (NCC) ...................... 48
O
Operation
Operation in Single Conversion Mode ............... 295
Operation Enable Bit
Operation Enable Bit ........................................ 381
Operation Mode
Operation in Asynchronous LIN Mode
(Operation Mode 3)............................. 388
Operation in Synchronous Mode
(Operation Mode 2)............................. 385
Operation Modes of 8/16-bit PPG...................... 262
UART0, UART1 Operation Modes ................... 322
Operation Status
Operation Status during Standby Mode .............. 148
Oscillation Stabilization Wait and Reset State
Oscillation Stabilization Wait and
Reset State ......................................... 129
Oscillation Stabilization Wait Time
Oscillation Stabilization Wait Time ........... 100, 160
Reset Causes and Oscillation Stabilization Wait
Times ................................................ 128
Oscillator
Connection of an Oscillator or an External Clock to the
Microcontroller................................... 101
Others
Others............................................................... 70
Output
Output Pin Functions of 16-bit Reload
Timer................................................. 234
Output Compare
Control Status Register of Output Compare
(Lower).............................................. 205
Control Status Register of Output Compare
(Upper) .............................................. 207
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