Reset Cause Bits - Fujitsu MB90390 Series Hardware Manual

7.5

Reset Cause Bits

A reset cause can be identified by reading the watchdog timer control register (WDTC).
■ Reset Cause Bits
As shown in Figure 7.5-1, a flip-flop is associated with each reset cause. The contents of the flip-flops are
obtained by reading the watchdog timer control register (WDTC). If the cause of a reset must be identified
after the reset has been cleared, the value read from the WDTC should be processed by the software and a
branch made to the appropriate program.
Watchdog timer
control register
(WDTC)
S : Set
R : Reset
Q : Output
F/F: Flip Flop
Figure 7.5-1 Block Diagram of Reset Cause Bits
RST pin
External reset
Power-on
request
detection
detection circuit
circuit
S S R S
R
F/F
F/F
Q
Q Q
Internal data bus
No periodic clear
RST="L"
Watchdog timer
reset generation
detection circuit
Clear
R
R
S
Delay
F/F F/F
circuit
Q
CHAPTER 7 RESETS
RST bit set
LPMCR, RST
bit write
detection circuit
Reading of
watchdog timer
control register
(WDTC)
133