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14.4
Underflow Operation of 16-bit Reload Timer
An underflow is defined for this timer as the time when the counter value changes from
"0000
" to "FFFF
H
H
counts.
■ Underflow Operation of 16-bit Reload Timer
If the RELD bit in the control register is "1" when the underflow occurs, the contents of the reload register
is loaded into the counter and counting continues. When RELD is "0", counting stops with the counter at
"FFFF
".
H
The UF bit in the control register is set when the underflow occurs. If the INTE bit is "1" at this time, an
interrupt request is generated.
Figure 14.4-1 shows the underflow operation of 16-bit reload timer.
Count clock
Counter
Data load
Underflow set
Count clock
Counter
Underflow set
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
". Therefore, an underflow occurs after (reload register setting + 1)
Figure 14.4-1 Underflow Operation of 16-bit Reload Timer
0000
H
[RELD=1]
0000
H
[RELD=0]
Reload data
-1
FFFF
H
-1
-1
233
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