Fujitsu MB90390 Series Hardware Manual page 721

Table D-2 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers (2/2)
Interrupt cause
Serial I/O
Sound generator
UART0 RX
UART0 TX
UART1 RX
UART1 TX
UART3 RX / (UART2 RX)
UART3 TX / (UART2 TX)
Flash memory
Delayed interrupt
2
Y1: An EI OS interrupt clear signal or EI
2
Y2: An EI OS interrupt clear signal or EI
2
N: An EI OS interrupt clear signal does not clear the interrupt request flag.
Note:
For a peripheral module having two interrupt causes for one interrupt number, an EI
clear signal clears both interrupt request flags.
2
When EI OS ends, an EI
number.
2
EI OS is activated when one of two interrupts assigned to an interrupt control register (ICR) is
caused while EI
specific to each interrupt cause is shared by two interrupts. Therefore, while one interrupt is enabled,
the other interrupt must be disabled.
2
EI OS
clear
Y1
N
Y2
Y1
Y2
Y1
Y2
Y1
N
N
2
OS register read access clears the interrupt request flag.
2
OS register read access clears the interrupt request flag. A stop request is issued.
2
OS clear signal is sent to every interrupt flag assigned to each interrupt
2
OS is enabled. This means that an EI
APPENDIX D List of Interrupt Vectors
Interrupt vector
Number Address
#33 FFFF78
H
34 FFFF74
H
35 FFFF70
H
36 FFFF6C
H
37 FFFF68
H
38 FFFF64
H
39 FFFF60
H
40 FFFF5C
H
41 FFFF58
H
42 FFFF54
H
2
OS descriptor that should essentially be
Interrupt control register
Number Address
0000BB
ICR11
H
0000BC
ICR12
H
0000BD
ICR13
H
0000BE
ICR14
H
0000BF
ICR15
H
2
OS interrupt
693