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CHAPTER 8 LOW-POWER CONTROL CIRCUIT
■ Release of Time-base Timer Mode
The low-power consumption control circuit releases the time-base timer mode when a reset is input or an
interrupt occurs.
●
Return by a reset
The time-base timer mode is initialized to the main clock mode by a reset.
Note:
The RST signal must be asserted for at least 100 μs in Main-Time-base Timer Mode.
●
Return by an interrupt
If an interrupt request of level seven or higher is issued from a peripheral circuit during the time-base timer
mode (IL2, IL1, and IL0 of the interrupt control register (ICR) do not indicate "111
consumption mode control circuit releases the time-base timer mode. After the mode is released, the
interrupt is handled as an ordinary interrupt. If the interrupt is accepted according to the setting of the I flag
of the condition code register (CCR), interrupt level mask register (ILM), or interrupt control register
(ICR), the CPU executes the interrupt processing. If the interrupt is not accepted, the CPU executes the
instruction following the instruction specifying the time-base timer mode.
Note:
When interrupt processing is executed, the CPU normally executes the instruction following the
instruction in which switching to the time-base timer mode has been specified. The CPU then
proceeds to interrupt processing. If the switching to the time-base timer mode and acceptance of an
external bus hold request occur at the same time, however, the CPU may proceed to interrupt
processing before executing the next instruction.
Wake up from Main-Time-base timer mode by interrupt is internally delayed up to 40 μs.
To set a pin to high impedance when the pin is shared by a peripheral function and a port in time-
base timer mode, disable the output of peripheral functions, and set the TMD bit of the low-power
consumption mode control register (LPMCR) to "0".
This applies to the following pins:
P03/IN3/OUT6, P05/IN5/OUT7, P06/OUT0, P07/OUT1, P10/OUT2, P11/OUT3, P12/OUT4,
P13/OUT5, P15/TOT0, P16/SGO, P17/SGA, P20/TX1, P31/TX0, P33/TOT1, P34/SOT0, P35/SCK0
152
"), the low-power
B
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