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CHAPTER 20 UART2, UART3
20.4.3
Serial Status Register (SSR2/SSR3)
This register checks the transmission and reception status and error status, and
enables and disables the transmission and reception interrupts.
■ Serial Status Register (SSR2/SSR3)
Figure 20.4-4 Configuration of the Serial Status Register (SSR2/SSR3)
bit
Address:
SSR3: 00351B
H
SSR2: 0035DB
H
R/W
:
Readable and writable
R
:
Flag is read only, write to it has
no effect
:
Initial value
354
15
14
13
12
11
10
R
R
R
R
R
R/W
R/W R/W
Initial value
9
8
0 0 0 0 1 0 0 0
bit8
TIE
0
Disables T r ansmission Interrupt
1
Enables T r ansmission Interrupt
bit9
RIE
0
Disables Reception Interrupt
1
Enables Reception Interrupt
bit10
BDS
0
send / receive LSB Þrst
1
send / receive MSB Þrst
bit11
TDRE
0
Transmission data register is full
1
Transmission data register is empty
bit12
RDRF
0
Reception data register is empty
1
Reception data register is full
bit13
FRE
0
No framing error occurred
1
A framing error occurred during reception
bit14
ORE
0
No overrun error occurred
1
An overrun error occurred during reception
bit15
PE
0
No parity error occurred
1
A parity error occurred during reception
B
Transmission Interrupt enable
Reception Interrupt enable
Bit direction setting
T r ansmission data register empty
Reception data register full
Framing error
Overrun error
Parity error
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