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CHAPTER 21 400 kHz I
2
21.3
I
C Interface Operation
2
The I
C bus executes communication using two bi-directional bus lines, the serial data
line (SDA) and serial clock line (SCL). The I
(SDA/SCL) corresponding to these lines, enabling wired logic applications.
■ Start Conditions
When the bus is free (BB = 0 in IBSR, MSS = 0 in IBCR), writing "1" to the MSS bit places the I
interface in master mode and generates a start condition.
If a "1" is written to it while the bus is idle (MSS = 0 and BB = 0), a start condition is generated and the
contents of the IDAR register (which should be address data) is sent.
Repeated start conditions can be generated by writing "1" to the SCC bit when in bus master mode and
interrupt status (MSS = 1 and INT = 1 in IBCR).
If a "1" is written to the MSS bit while the bus is in use (BB = 1 and TRX = 0 in IBSR; MSS = 0 and INT = 0
in IBCR), the interface waits until the bus is free and then starts sending.
If the interface is addressed as slave with write access (data reception) in the meantime, it will start sending
after the transfer ended and the bus is free again. If the interface is sending data as slave in the meantime, it
will not start sending data if the bus of free again. It is important to check whether the interface was
addressed as slave (MSS = 0 in IBCR and AAS = 1 in IBSR), sent the data byte successfully (MSS = 1 in
IBCR) or failed to send the data byte (AL = 1 in IBSR) at the next interrupt.
Writing "1" to the MSS bit or SCC bit in any other situation has no significance.
■ Stop Conditions
Writing "0" to the MSS bit in master mode (MSS = 1 and INT = 1 in IBCR) generates a stop condition and
places the device in slave mode. Writing "0" to the MSS bit in any other situation has no significance.
After clearing the MSS bit, the interface tries to generate a stop condition which might fail if another
master pulls the SCL line low before the stop condition has been generated. This will generate an interrupt
after the next byte has been transferred!
432
2
C INTERFACE
2
C interface has two open-drain I/O pins
2
C
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