Fujitsu MB90390 Series Hardware Manual page 391

Table 20.4-6 Function of Each Bit of the Extended Communication Control Register (ECCR2/ECCR3)
Bit name
bit7 -
LBR: Generating
bit6
LIN synch break bit
MS:
bit5 Master/Slave mode
selection bit
SCDE:
bit4 Serial clock delay
enable bit
SSM:
bit3 Start/Stop bit mode
enable
bit2 Undefined bit
RBI:
bit1 Reception bus idle
flag bit
TBI:
bit0 Transmission bus idle
flag bit
This bit is undefined. Always write "0".
Writing a "1" to this bit generates a LIN synch break of the length selected by the LBL0/
LBL1 bits of the ESCR2/ESCR3, if operation mode 3 is selected. Setting to "0" in
operation mode 0.
This bit selects master or slave mode of UART2, UART3 in synchronous mode 2. If
master is selected UART2, UART3 generates the synchronous clock by itself. If slave
mode is selected,
UART2, UART3 receives external serial clock.
This bit is fixed to "0" in operation mode 0, 1 and 3.
Note:
If slave mode is selected, the clock source must be external and set to "One-to-One"
(SMR2/SMR3: SCKE = 0, EXT = 1, OTO = 1).
If this bit is set the serial output clock is delayed as shown in Figure 20.7-5 if UART2, 3
operates in master mode 2.
Note:
Figure 20.7-5 shows the behavior of MB90V390HA/MB90V390HB/MB90394HA
(the delay is one half serial clock cycle). For MB90V390H/MB90F394H(A), the
delay is one machine clock cycle.
This bit adds start and stop bits to the synchronous data format in operation mode 2. It is
ignored in mode 0, 1, and 3.
Undefined bit. Reading value is undefined. Always write to "0".
This bit is "1" if there is no reception activity on the SIN2/SIN3 pin and it is kept at "1".
Do not use this bit in mode 2 when SSM=0.
This bit is "1" if there is no transmission activity on the SOT2/SOT3 pin.
Do not use this bit in mode 2 when SSM=0.
CHAPTER 20 UART2, UART3
Function
363