Block Diagram Of The Low-Power Consumption Control Circuit - Fujitsu MB90390 Series Hardware Manual

8.2 Block Diagram of the Low-Power Consumption Control
Circuit
The low-power consumption control circuit consists of the following seven blocks:
• CPU intermittent operation selector
• Standby control circuit
• CPU clock control circuit
• Peripheral clock control circuit
• Pin high-impedance control circuit
• Internal reset generation circuit
• Low-power consumption mode control register (LPMCR)

■ Block Diagram of the Low-power Consumption Control Circuit

Figure 8.2-1 shows a block diagram of the low-power consumption control circuit.
Figure 8.2-1 Block Diagram of the Low-power Consumption Control Circuit
RST Pin
Interrupt
clearing
CS2
Bit8 of PLL and
Special Configulation
Control Register
(PSCCR)
Pin
X0
Pin
X1
System clock
generation circuit
Low-Power Consumption Mode Control Register (LPMCR)
STP SLP SPL RST TMD CG1 CG0
Machine clock
Clock
Selector
PLL multiplier circuit
Clock Selection register (CKSCR)
Mainclock
Divide- Divide-
by-2 by-1024
HCLK
Time-base Timer
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
Re-
served
intermittent
cycle
selector
CPU intermittent
operation
selector
Standby
control
circuit
Oscillation stabilization wait time clear
2
- MCM WS1 WS0 - MCS CS1 CS0
Divide- Divide-
by-2 by-4
Watchdog Timer
Pin high-
Pin Hi-Z
impedance
control
control circuit
Internal reset
Internal
generation
reset
circuit
CPU clock
CPU
control
clock
circuit
Stop and
sleep signals
Stop signal
Peripheral
Peripheral
clock control
clock
circuit
Oscillation
stabilization
wait time
interval selector
2
Divide- Divide- Divide-
by-4 by-4 by-2
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