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2
21.2.6
I
C Data Register (IDAR)
Data Register for the 400 kHz I
2
■ I
C Data Register (IDAR)
R/W
:
Readable and writable
2
■ I
C Data Register Contents
Table 21.2-7 Function of Each Bit of the I
Bit name
D7 to D0:
bit7 to bit0
Data bits
2
C Interface.
7
6
5
4
bit
Address:
D7 D6 D5 D4 D3 D2
0035A8
H
R/W R/W R/W R/W
2
C Data Register
The data register is used in serial data transfer, and transfers data MSB first. This
register is double buffered on the write side, so that when the bus is in use (BB = 1),
write data can be loaded to the register for serial transfer. The data byte is loaded
into the internal transfer register if the INT bit in the IBCR register is being
cleared or the bus is idle (BB = 0 in IBSR). In a read access, the internal register is
read directly, therefore received data values in this register are only valid if INT=
1 in the IBCR register.
CHAPTER 21 400 kHz I
3
2
1
0
IDAR
D1 D0
Initial value
0 0 0 0 0 0 0 0
R/W
R/W
R/W R/W
Function
2
C INTERFACE
B
427
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