Serial I/O Prescaler (Cdcr) - Fujitsu MB90390 Series Hardware Manual

22.3

Serial I/O Prescaler (CDCR)

The Serial I/O Prescaler provides the shift clock for the Serial I/O.
The operation clock for the Serial I/O is obtained by dividing the machine clock. The
Serial I/O is designed so that a constant baud rate can be obtained for a variety of
machine clocks by the use of the communication prescaler. The CDCR register controls
the machine clock division.
■ Serial I/O Prescaler (CDCR)
bit15
Address
00002F
H
R/W : Readable and writable
X : Undefined value
- : Undefined
: Initial value
Note:
When the division ratio is changed, allow two cycles for the clock to stabilize before starting
communication.
Figure 22.3-1 Configuration of the Serial I/O Prescaler (CDCR)
bit14 bit13 bit12
MD - NEG -
- -
R/W R/W
bit11 bit10 bit9 bit8
DIV3 DIV2 DIV1 DIV0
R/W R/W R/W R/W
DIV3 to
Machine Clock Division Ratio bits
DIV0
0000 Division ratio: div = 1
B
0001 Division ratio: div = 2
B
0010 Division ratio: div = 3
B
0011 Division ratio: div = 4
B
0100 Division ratio: div = 5
B
0101 Division ratio: div = 6
B
0110 Division ratio: div = 7
B
0111 Division ratio: div = 8
B
1xxx reserved
B
NEG Negative Clock Operation bit
0 Normal operation
1 The shift clock signal is inverted
MD Machine Clock Divide Mode Select bit
0 The Serial I/O Prescaler is disabled.
1 The Serial I/O Prescaler is enabled.
CHAPTER 22 SERIAL I/O
Initial value
0 X 0 X 0 0 0 0
B
445