Fujitsu MB90390 Series Hardware Manual page 300

CHAPTER 17 DTP/EXTERNAL INTERRUPTS
Note:
If multiple external interrupt request outputs are enabled (ENIR: EN3 to EN0=1), only the bits for
which the CPU accepts an interrupt (bits for which "1" was set in ER3 to ER0) are cleared. No other
bits must be cleared unconditionally.
• The value of DTP/external interrupt source bit (EIRR: ER) is valid only when the corresponding
DTP/external interrupt enable bit (ENIR: EN) is set to "1". In the case that DTP/external interrupt
isn't allowed (ENIR: EN = 0), DTP/external interrupt source bit could be set regardless of the
possibility of DTP/external interrupt source.
• Clear the corresponding DTP/external interrupt source bit (EIRR: ER) right before DTP/external
interrupt is allowed (ENIR: EN = 1).
■ Request Level Setting Register (ELVR: External Level Register)
Address : 000032
Address : 000033
ELVR defines the request event at the external pin. Each pin is assigned two bits as described in Table
17.2-1. If a request is detected by the input level, the interrupt flag is set as long as the input is at the
specified level even after the flag is reset by software.
Table 17.2-1 Interrupt Request Detection Factor for External Pins
272
7 6 5
bit
LB3 LA3 LB2
H
R/W R/W
R/W
bit
15 14 13
LB7 LA7 LB6
H
R/W R/W
R/W
LBx LAx
0 0
0 1
1 0
1 1
4 3 2
LA2 LB1 LA1
R/W R/W R/W
12 11 10
LA6 LB5 LB5
R/W R/W R/W
Interrupt request detection factor
"L" level pin input
"H" level pin input
Rising edge pin input
Falling edge pin input
1 0 Initial value
LB0 LA0 00000000
R/W R/W
Initial value
9 8
00000000
LB4 LA4
R/W R/W
B
B