Table of Contents
Advertisement
CHAPTER 11 TIME-BASE TIMER
11.1
Outline of Time-base Timer
The time-base timer consists of an 18-bit time-base counter and a control register. The
18-bit time-base counter divides the system clock. The time-base timer issues
interrupts at specified intervals based on carry signals of the time-base counter.
■ Outline of Time-base Timer
When the power is turned on, the time-base counter can be cleared to all zeroes by setting the stop mode or
by software (writing "0" to the TBR bit). The time-base counter is incremented while the source oscillation
is input.
The time-base counter can be used as a timer for supplying clock to the watchdog timer or for oscillation
stabilization wait time.
■ Block Diagram of Time-base Timer
Figure 11.1-1 shows a block diagram of the time-base timer.
WTE
WT1
WT0
1
f/2
2
Power-on
reset
Clear
control
STOP
mode
TBR
TBC1
TBC0
WS1
WS0
178
Figure 11.1-1 Block Diagram of Time-base Timer
Time-base counter
2
10
17
1/2
to 1/2
Selector
Two-bit
Selector
counter
1
1
1
1
11
12
13
14
2
2
2
2
TBOF
TBOF
Selector
EI OS
Time-base division output
Osciliation stabilization wait completion signal
Output enable
Reset
control
1
1
1
1
15
16
17
18
2
2
2
IRQ
Clear
2
Reset
Advertisement
Table of Contents
