Fujitsu MB90390 Series Hardware Manual page 288

CHAPTER 16 8/16-BIT PPG
Table 16.3-3 Bit Function Description of the Clock Select Register (PPG01)
Bit name
PCS2 to PCS0:
bit7 to bit5 Count clock selection
bit
PCM2 to PCM0:
bit4 to bit2 Count clock selection
bit
260
These bits select the operation clock for the down counter of Channel 1 as described
below.
Note:
In 8-bit prescaler + 8-bit PPG mode or in 16-bit PPG mode, ch.1 PPG operates in
response to a counter clock from ch.0. Therefore, the setting in these bits has no
effect.
PCS2 PCS1 PCS0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 1 1
These bits select the operation clock for the down counter of Channel 0 as described
below.
PCM2 PCM1 PCM0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 1 1
Function
Operation mode
Peripheral Clock (62.5 ns machine clock, 16 MHz)
Peripheral Clock/2 (125 ns machine clock, 16 MHz)
Peripheral Clock/4 (250 ns machine clock, 16 MHz)
Peripheral Clock/8 (500 ns machine clock, 16 MHz)
Peripheral Clock/16 (1 μs machine clock, 16 MHz)
Clock input from the time-base timer
(128 μs, 4 MHz source oscillation)
Operation mode
Peripheral Clock (62.5 ns machine clock, 16 MHz)
Peripheral Clock/2 (125 ns machine clock, 16 MHz)
Peripheral Clock/4 (250 ns machine clock, 16 MHz)
Peripheral Clock/8 (500 ns machine clock, 16 MHz)
Peripheral Clock/16 (1 μs machine clock, 16 MHz)
Clock input from the time-base timer
(128 μs, 4 MHz source oscillation)