Fujitsu MB90390 Series Hardware Manual page 155

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External reset
An external reset is generated by the "L" level input to an external reset pin (RST pin). The minimum
required period of the "L" level is 16 machine cycles (16/φ). The oscillation stabilization wait time is not
required for external resets.
In the MB90390 series the external reset has to be Min 100 μs for wake-up from Main-Time base timer
mode and Min 100 μs + Oscillation time of oscillator + 16 machine cycles for wake-up from Stop mode.
Refer to the AC characteristics section of the data sheet.
Reference:
If the reset cause is generated during a write operation (during the execution of a transfer instruction
such as MOV), the CPU waits for the reset to be cleared after completion of the instruction only for
reset requests via the RST pin. Therefore, the normal write operation is completed even though a reset
is input concurrently.
Note that a reset may prevent the data transfer requested by a string-processing instruction (such as
MOVS) from being completed because the reset is accepted before a specified number of bytes are
transferred.
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Software reset
A software reset is an internal reset generated by writing "0" to the RST bit of the low-power consumption
mode control register (LPMCR). The oscillation stabilization wait time is not required for a software reset.
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Watchdog timer reset
A watchdog timer reset is generated by a watchdog timer overflow that occurs when "0" is written to the
WTE bit of the watchdog timer control register (WDTC) within a given time after the watchdog timer is
activated. The oscillation stabilization wait time can be set by the clock selection register (CKSCR).
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Power-on reset
A power-on reset is generated when the power is turned on. In this case the oscillation stabilization wait
time is fixed to at 2
stabilization wait time has elapsed, the reset is executed.
Reference Definition of clocks
HCLK: Oscillation clock
MCLK: Main clock
φ: Machine clock (CPU operating clock)
1/φ: Machine cycle (CPU operating clock period)
See "CHAPTER 5 CLOCKS", for details on machine clocks.
18
HCLK cycles (approx. 65.54 ms at 4MHz source oscillation). When the oscillation
CHAPTER 7 RESETS
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