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A
A
Accumulator (A)................................................ 39
A/D Control Status Register
A/D Control Status Register 0 (ADCS0) ............ 290
Upper Bits of the A/D Control Status Register 1
(ADCS1)............................................ 288
A/D Conversion
A/D Conversion Data Protection Function.......... 298
A/D Data Register
A/D Data Register (ADCR0, ADCR1) ............... 292
Acceptance Filter
Setting Acceptance Filter .................................. 508
Acceptance Filtering
Acceptance Filtering ........................................ 504
Acceptance Mask Registers
Acceptance Mask Registers 0 and 1
(AMR0 and AMR1) ............................ 493
Acceptance Mask Select Register
Acceptance Mask Select Register (AMSR)......... 491
Accumulator
Accumulator (A)................................................ 39
Activation
Activation ....................................................... 188
ADCR
A/D Data Register (ADCR0, ADCR1) ............... 292
ADCS
A/D Control Status Register 0 (ADCS0) ............ 290
Upper Bits of the A/D Control Status Register 1
(ADCS1)............................................ 288
Address Match Detection Function
Block Diagram of the Address Match Detection
Function............................................. 544
Operation of the Address Match Detection
Function............................................. 547
System Configuration Example of the Address Match
Detection Function .............................. 548
Addressing
Addressing ...................................................... 623
Addressing Slaves............................................ 434
Direct Addressing ............................................ 625
Indirect Addressing .......................................... 631
ADER
Lower Bits of the Analog Input Enable Register
(ADER0)............................................ 287
Upper Bits of the Analog Input Enable/A/D Converter
Select Register (ADER1) ..................... 287
Alternative Mode
Alternative Mode ............................................. 559
Amplitude Data Register
Amplitude Data Register................................... 540
AMR
Acceptance Mask Registers 0 and 1
(AMR0 and AMR1).............................493
AMSR
Acceptance Mask Select Register (AMSR) .........491
Analog Input Enable Register
Analog Input Enable Registers ...................175, 285
Lower Bits of the Analog Input Enable Register
(ADER0) ............................................287
Analog Input Enable/A/D Converter Select Register
Upper Bits of the Analog Input Enable/A/D Converter
Select Register (ADER1)......................287
Application Example
Application Example ........................................334
Arbitration
Arbitration .......................................................434
Asynchronous LIN Mode
Operation in Asynchronous LIN Mode
(Operation Mode 3) .............................388
Asynchronous Mode
Operation in Asynchronous Mode ......................382
B
Bank Addressing Types
Bank Addressing Types.......................................33
Bank Select Prefix
Bank Select Prefix ..............................................47
BAP
Buffer Address Pointer (BAP) .............................74
Baud Rate
Calculating the Baud Rate .................................375
UART2, UART3 Baud Rate Selection ................373
Baud Rate Generator Register
Bit Configuration of Baud Rate Generator Register
(BGR02/03 and BGR12/13)..................364
BGR
Bit Configuration of Baud Rate Generator Register
(BGR02/03 and BGR12/13)..................364
Bidirectional Communication
Bidirectional Communication Function...............393
Bit Timing
Setting Bit Timing ............................................508
Bit Timing Register
Bit Timing Register (BTR) ................................477
Bit Timing Register (BTR) Contents ..................477
Block Diagram
16-bit Free-run Timer Block Diagram.................196
Block Diagram of 16-bit I/O Timer ....................193
Block Diagram of 8/16-bit PPG .........................250
Block Diagram of CAN Controller .....................457
Block Diagram of Delayed Interrupt.....................82
Block Diagram of DTP/External Interrupts .........270
697
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