Control Status Register Of Output Compare - Fujitsu MB90390 Series Hardware Manual

13.4.2

Control Status Register of Output Compare

The control status register sets the operation mode of output compare, starts and stops
output compare, controls interrupts, and sets the external output pins.
■ Control Status Register of Output Compare (Lower)
Figure 13.4-3 Control Status Register of Output Compare (OCS0/OCS2/OCS4/OCS6)
bit 7
Address:
000058
H
ICPm
00005A
H
00005C
R/W R/W R/W R/W
H
003568
H
R/W : Readable and writable
X : Undefined value
- :
Undefined
: Initial value
6 5 4 3 2 1
ICEm ICEn CSTm
ICPn
- - R/W R/W
OCS0
OCS2
0
OCS4 OCS6
CSTn
Initial value
0 0 0 0 X X 0 0
B
bit 0
CSTn Comparison with timer for unit n
0 Compare operation disabled for unit n
1 Compare operation enabled for unit n
bit 1
CSTm Comparison with timer for unit m
0 Compare operation disabled for unit m
1 Compare operation enabled for unit m
bit 4
Compare interrupt enable for unit n
ICEn
0 Output compare interrupt disabled for unit n
1 Output compare interrupt enabled for unit n
bit 5
Compare interrupt enable for unit m
ICEm
0 Output compare interrupt disabled for unit m
1 Output compare interrupt enabled for unit m
bit 6
ICPn Compare match enable for unit n
0 No compare match for unit n
1 Compare match for unit n
bit 7
ICPm Compare match enable for unit m
0 No compare match for unit m
1 Compare match for unit m
CHAPTER 13 16-BIT I/O TIMER
n = 0, 2, 4, 6 m = 1, 3, 5, 7
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