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Clearing the reset cause bits
The reset cause bits are cleared only when the watchdog timer control register (WDTC) is read. Any bit
corresponding to a reset cause that has already been generated is not cleared even though another reset is
generated (a setting of "1" is retained).
Note:
If the power is turned on under conditions where no power-on reset occurs, the value in WDTC
register may not be guaranteed.
CHAPTER 7 RESETS
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