Fujitsu MB90390 Series Hardware Manual page 160

CHAPTER 7 RESETS
■ Mode Fetch
When the reset is cleared, the CPU transfers the reset vector and the mode data to the appropriate registers
in the CPU core by hardware. The reset vector and mode data are allocated to the four bytes from
"FFFFDC
cleared and then fetches the reset vector and mode data. Using mode fetching, the CPU can begin
processing at the address indicated by the reset vector.
Figure 7.4-2 shows the transfer of the reset vector and mode data.
FFFFDF
FFFFDE
FFFFDD
FFFFDC
●
Mode data (address: FFFFDF
Only a reset operation changes the contents of the mode register. The mode register setting is valid after a
reset operation. See Section "9.3 Mode Data of Memory Access Mode", for details on mode data.
●
Reset vector (address: FFFFDC
The execution start address after the reset operation ends is written as the reset vector. Execution starts at
the address contained in the reset vector.
Note:
For MB90F394H(A), the reset vector and the mode data have different predetermined values by the
hardwired logic.
For more information, refer to Section "28.9 Reset Vector Address in Flash Memory".
132
" to "FFFFDF ". The CPU outputs these addresses to the bus immediately after the reset is
H H
Figure 7.4-2 Transfer of Reset Vector and Mode Data
Memory space
Mode data
H
Bit23 to bit16 of reset vector
H
Bit15 to bit8 of reset vector
H
Bit7 to bit0 of reset vector
H
)
H
to FFFFDE
H
2
F MC-16LX CPU core
Reset
sequence
)
H
Mode
register
Micro-
ROM
PCB
PC