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CHAPTER 5 CLOCKS
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System clock generation circuit
The system clock generation circuit generates an oscillation clock (HCLK) from an external oscillator
attached to it. Alternatively, an external clock can be input to this circuit.
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PLL multiplier circuit
The PLL multiplier circuit multiplies the oscillation clock frequency through PLL oscillation and supplies a
clock whose frequency is a multiple of the oscillation clock frequency to the CPU clock selector.
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Clock selector
From among the main clock and six different PLL clocks, the clock selector selects the clock that is
supplied to the CPU and peripheral clock control circuits.
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Clock selection register (CKSCR)
The clock selection register is used to switch between the oscillation clock and a PLL clock and is also used
to select an oscillation stabilization wait time and a PLL clock multiplier.
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Oscillation stabilization wait time selector
This oscillation stabilization wait time selector selects an oscillation stabilization wait time for the
oscillation clock when the stop mode is released. Selection is made from among four different time-base
timer outputs. In all other cases, an oscillation stabilization wait time is not selected.
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