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Reference: Main changes (Rev.2 → Rev.3)
Page
● Crystal Oscillator Circuit is changed.
(Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. is
added.)
24
● Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs is changed.
((turning on/off the analog and digital power supplies simultaneously is acceptable) is deleted.)
● Note on operation during PLL clock mode is changed.
Figure 3.1-2 Overview of Software Interrupts is changed.
55
(ILM : Interrupt level mask register → S :Stack flag)
Notes is changed.
59
(• ICS1 and ICS0 are valid for write only. S1 and S0 are valid for read only. is added.)
(<Additional information> is added.)
Figure 3.4-2 Register Saving During Interrupt Processing is changed.
63
(DPB → DTB)
Figure 3.5-2 Registers Saved in Stack is changed.
68
(DPB → DTB)
Figure 3.6-1 Occurrence and Release of Software Interrupt is changed.
70
(ILM : Interrupt level mask register → S :Stack flag)
● When data transfer continues (when the stop condition is not satisfied) is changed.
((Table 3.8-1 "Execution time when the extended EI
78
tion values for extended EI
cycles)
103
Summary of 5.7 Output of the main clock HCLK and HCLKX is changed.
CHAPTER 6 CLOCK MODULATOR
105
Notes is changed.
Table 6.3-1 Function of Each Bit of the Clock Modulator Control Register (3/3)
112
Function of bit1 is changed.
(6 ms → 6 µs)
Table 6.3-2 States of the Modulator is changed.
(modulator power on, waiting modulator startup time (> 6 ms) →
113
modulator power on, waiting modulator startup time (> 6 µs))
Figure 6.3-3 Modulation Parameter Register is changed.
(CMPRL (upper) → CMPRH (upper))
114
(XX0000010
Figure 8.2-1 Block Diagram of the Low-power Consumption Control Circuit is changed.
141
(Osc. stab. wait clear → Oscillation stabilization wait time clear)
158
8.7 Status of Pins in Standby Mode and during Reset is added.
■ Analog Input Enable Registers
Note is changed.
175
(ANIN 0 to 7 → AN0 to AN7)
(ANIN 8 to 14 → AN8 to AN14)
184
Figure 12.1-1 Watchdog Timer Block Diagram is changed.
■ State Transition Diagram of the Watchdog Timer is added.
187
■ Watchdog Counter is changed.
■ Watchdog Stop is changed.
188
■ Watchdog Deactivation is added.
■ Watchdog Timer Behavior in Stop Mode, Time-base Timer Mode, and Sleep Mode is added.
■ Watchdog Timer Behavior at Reset is added.
189
Changes (For details, refer to main body.)
2
OS execution time") machine cycles → ((Table 3.8-1 + Table 3.8-2) machine
→ XX000010
)
B
B
2
OS continues" + Table 3.8-2 "Data transfer compensa-
xvi
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