Clock Mode - Fujitsu MB90390 Series Hardware Manual

5.4

Clock Mode

Two clock modes are provided: main clock mode and PLL clock mode.
■ Main Clock Mode and PLL Clock Mode
●
Main clock mode
In main clock mode, a clock whose frequency is the oscillation clock frequency divided by 2 is used as the
operating clock for the CPU and peripheral resources, and the PLL clocks are disabled.
●
PLL clock mode
In PLL clock mode, a PLL clock is used as the operating clock for the CPU and peripheral resources. A
PLL clock multiplier is selected with the clock selection register (CKSCR: CS1 and CS0) and the PLL and
special configuration control register (PSCCR: CS2).
■ Clock Mode Transition
Transition among main clock mode, and PLL clock mode is performed by writing to the MCS bit of the
clock selection register (CKSCR).
●
Transition from main clock mode to PLL clock mode
When the MCS bit of the clock selection register (CKSCR) is rewritten from "1" to "0" in main clock
mode, switching from the main clock to a PLL clock occurs after the PLL clock oscillation stabilization
wait time (2
●
Transition from PLL clock mode to main clock mode
When the MCS bit of the clock selection register (CKSCR) is rewritten from "0" to "1" in PLL clock mode,
switching from the PLL clock to the main clock occurs when the edges of the PLL clock and the main
clock coincide (after 1 to 8 PLL clocks).
Note:
Even though the MCS bit of the clock selection register (CKSCR) is rewritten, machine clock
switching does not occur immediately. When operating a resource that depends on the machine
clock, confirm that machine clock switching has been performed by referring to the MCM bit of the
clock selection register (CKSCR) before operating the resource.
In attempting to switch the clock mode, do not attempt to switch to another clock mode or low-power
consumption mode until the first switching is completed. The MCM bit of the clock selection register
(CKSCR) indicate that switching is completed.
■ Selection of a PLL Clock Multiplier
Writing a value from "00
"0" or "1" to the CS2 bit of the PLL and special configuration control register (PSCCR) selects a PLL clock
multiplier of 1 to 4, 6 or 8 (refer to Table 5.3-1 bit8 and bit9).
14
/HCLK).
" to "11 " to the CS1 and CS0 bits of the clock selection register (CKSCR) and
B B
CHAPTER 5 CLOCKS
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