Control Status Register - Fujitsu MB90390 Series Hardware Manual

CHAPTER 13 16-BIT I/O TIMER
13.3.2

Control Status Register

The control status register sets the operation mode of the 16-bit free-run timer, starts
and stops the 16-bit free-run timer, and controls interrupts.
■ Control Status Register of Free-run Timer (Lower)
Figure 13.3-3 Control Status Register of Free-run Timer (TCCSL0/TCCSL1)
Address: bit 7
00352E
H
IVF
00353E
H
R/W R/W R/W R/W R/W
R/W : Readable and writable
: Initial value
198
6 5 4 3 2 1
IVFE
STOP MODE CLR CLK2 CLK1 CLK0
R/W R/W R/W
TCCSL0/TCCSL1
0
Initial value
0 0 0 0 0 0 0 0
bit 2 bit1 bit 0
CLK2 CLK1 CLK0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
bit 3
CLR
Read
0
read always "0"
1
bit 4
MODE Set Reset condition of timer
0 Initialization by reset or clear bit
1 Init. by reset, clear bit, or compare reg. 0 (4)
bit 5
STOP Stop the timer
0 Counter enabled
1 Counter disabled (stop)
bit 6
IVFE Interrupt enable bit
0 Interrupt disabled
1 Interrupt enabled
bit 7
Interrupt request flag bit
IVF
Read
0 No interrupt
1 Interrupt request
B
Count Clock Selection
φ
φ / 2
φ / 4
φ / 8
φ / 16
φ / 32
φ / 64
φ / 128
φ = MCU clock
Clear Timer
Write
no effect
clear timer to "0000 "
B
Write
clear this bit
no effect