Fujitsu MB90390 Series Hardware Manual page 443

■ Bus Control Register (IBCR) Contents
Table 21.2-2 Function of Each Bit of the Bus Control Register (IBCR) (1/3)
Bit name
BER:
bit15
Bus error bit
BEIE:
Bus error
bit14
interrupt enable
bit
SCC
bit13 Start condition
continue bit
This bit is the bus error interrupt flag. It is set by the hardware and cleared by the user.
It always reads "1" in a Read-Modify-Write (RMW) instruction access.
Write access:
"0": Clear bus error interrupt flag
"1": No effect
Read access:
"0": No bus error detected
"1": One of the error conditions described below detected
When this bit is set, the EN bit in the ICCR register is cleared, the I
pause status, data transfer is interrupted and all bits in the IBSR and the IBCR registers
except BER and BEIE are cleared. The BER bit must be cleared before the interface
may be reenabled.
This bit is set to "1" if:
- start or stop conditions are detected at wrong places: during an address data transfer or
during the transfer of the bits two to nine (acknowledge bit)
- a ten bit address header with read access is received before a ten bit write access
This bit enables the bus error interrupt. It only can be changed by the user.
"0": Bus error interrupt disabled
"1": Bus error interrupt enabled
Setting this bit to "1" enables MCU interrupt generation when the BER bit is set to "1".
This bit is used to generate a repeated start condition. It is write only - it always reads
"0".
"0": No effect
"1": Generate repeated start condition during master transfer
A repeated start condition is generated if a "1" is written to this bit while an interrupt in
master mode (MSS = 1 and INT = 1) and the INT bit is cleared automatically.
CHAPTER 21 400 kHz I
Function
2
C INTERFACE
2
C interface goes to
415