Counter Operation State - Fujitsu MB90390 Series Hardware Manual

14.6

Counter Operation State

The counter state is determined by the CNTE bit in the control register and the internal
WAIT signal. Available states are: CNTE = 0 and WAIT = 1 (STOP state), CNTE = 1 and
WAIT = 1 (WAIT state for trigger), and CNTE = 1 and WAIT = 0 (RUN state).
■ Counter Operation State
Figure 14.6-1 shows the counter state transitions.
Reset
CNTE=0
WAIT CNTE=1, WAIT=1
TIN pin: Only trigger input enabled
OUTE=0: General-purpose port
TOT pin:
OUTE=1: Initial value output
Counter: Retains the value while
counting stopped.
Value undefined after reset until
load.
External trigger from TIN
*: Before using TIN pin, the corresponding bit of the DDR must be set to "0"
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
Figure 14.6-1 Counter State Transitions
STOP CNTE=0, WAIT=1
TIN pin: Input disabled
OUTE=0: General-purpose port
TOT pin:
OUTE=1: Initial value output
Counter: Retains the value while
counting stopped.
Value undefined after reset.
CNTE=1
TRG=0
*
RELD • UF
TRG=1
LOAD CNTE=1, WAIT=0
Load contents of the reload
register to the counter.
State transitions by hardware
State transitions by external input
State transitions by register access
CNTE=0
CNTE=1
TRG=1
RUN CNTE=1, WAIT=0
TIN pin: Functions as TIN pin
OUTE=0: General-purpose port
TOT pin:
OUTE=1: Function as TOT pin
Counter: Running
TRG=1
RELD UF
External trigger from TIN
*
Load complete
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