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CHAPTER 20 UART2, UART3
■ Transmission Interrupt Request Generation Timing
If the TDRE flag is set to "1" when a transmission interrupt is enabled (SSR2/SSR3: TIE=1), transmission
interrupt request is generated.
Note:
A transmission completion interrupt is generated immediately after the transmission interrupt is
enabled (TIE=1) because the TDRE bit is set to "1" as its initial value. TDRE is a read-only bit that
can be cleared only by writing new data to the transmission data register (TDR2/TDR3). Carefully
specify the transmission interrupt enable timing.
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