Transmission Interrupt Generation And Flag Set Timing - Fujitsu MB90390 Series Hardware Manual

20.5.2

Transmission Interrupt Generation and Flag Set Timing

A transmission interrupt is generated when the transmission data is transferred from
transmission data register (TDR2/TDR3) to transmission shift register and started.
■ Transmission Interrupt Generation and Flag Set Timing
A transmission interrupt is generated, when the next data to be sent is ready to be written to the
Transmission Data Register (TDR2/TDR3), i. e. the TDR2/TDR3 is empty, and the transmission interrupt
is enabled by setting the Transmission Interrupt Enable (TIE) bit of the Serial Status Register (SSR2/SSR3)
to "1".
The Transmission Data Register Empty (TDRE) flag bit of the SSR2/SSR3 indicates an empty TDR2/
TDR3. Because the TDRE bit is "read only", it only can be cleared by writing data into TDR2/TDR3.
The following figure demonstrates the transmission operation and flag set timing for the four modes of
UART2, UART3.
Mode 0, 1, 2 (SSM=1) or 3:
write to TDR2/TDR3
TDRE
serial output
Mode 2 (SSM = 0):
write to TDR2/TDR3
TDRE
serial output
ST: Start bit
Note:
The example in Figure 20.5-3 does not show all possible transmission options for mode 0. Here it is:
"8p1" (p = "E" [even] or "O" [odd]). Parity is not provided in mode 3 or 2, if SSM = 0.
Figure 20.5-3 Transmission Operation and Flag Set Timing
transmission interrupt occurs
ST D0 D1 D2 D3 D4 D5 D6 D7
transmission interrupt occurs
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4
D0 ... D7: data bits P: Parity
transmission interrupt occurs
P
SP ST D0 D1 D2 D3 D4 D5 D6 D7
AD
transmission interrupt occurs
SP: Stop bit AD: Address/data selection bit (mode1)
CHAPTER 20 UART2, UART3
P
SP
AD
371