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■ Chip Erase/Sector Erase Command Sequence
Figure C-4 Timing Diagram for Write access (Chip Erasing/sector Erasing)
AQ18
to
7AAAA
AQ0
CE
t
GHWL
OE
WE
t
CS
DQ7
to
DQ0
V
CC
t
VCS
Note:
SA is the sector address at sector erasing. 7AAAA
t
t
AS
AH
75555
7AAAA
H
H
t
WP
t
WPH
t
DH
AA
55
H
H
t
DS
APPENDIX C Timing Diagrams in Flash Memory Mode
7AAAA
75555
H
H
80
AA
H
H
(or 6AAAA
H
H
SA*
H
55
10
/30
H
H
H
) is the address at chip erasing.
685
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