A/D Control Status Register 1 (Adcs1) - Fujitsu MB90390 Series Hardware Manual

CHAPTER 18 8/10-BIT A/D CONVERTER
18.4.2

A/D Control Status Register 1 (ADCS1)

A/D control status register 1 (ADCS1) selects activation by software or activation
trigger, enables or disables interrupt requests, and indicates interrupt request status
and whether conversion is halted or in progress.
■ Upper Bits of the A/D Control Status Register 1 (ADCS1)
Figure 18.4-4 Configuration of the A/D Control Status Register 1 (ADCS1)
bit
Address
000035 BUSY
H
R/W
: Readable and writable
R/W
: Write only
W
: Undefined
-
: Initial value
288
15 14 13 12 11
INT INTE PAUS STS1
R/W R/W R/W R/W
10 9 8 7
STS0 STRT
Reserved
R/W W R/W
Reserved
Always write "0" to this bit.
STRT
(
valid only when activated by software (ADC2: EXT= 0))
Does not activate the A/D conversion.
0
Activate the A/D conversion function.
1
STS1 STS0
0 0 Activation by software.
0 1 Activation by external trigger or software.
Activation by 16-bit reload timer 1 output
0
1
or software.
Activation by external trigger, 16-bit
1
1
reload timer 1 output, or software.
PAUS
(valid only when EI
0 A/D conversion is not halted.
A/D conversion is halted.
1
INTE Interrupt request enable bit
0 Disables interrupt request output.
1 Enables interrupt request output.
Interrupt request flag bit
INT
Reading
0
A/D conversion has not been completed.
1 A/D conversion has been completed.
BUSY
Reading
0
A/D conversion is halted.
1
A/D conversion is in progress.
0
Initial value
(ADCS0)
00000000
B
Reserved bit
A/D conversion activation bit
A/D activation select bit
Halt flag bit
2
OS is used)
Writing
Clears this bit.
No change, no effect on other bits.
Busy bit
Writing
Stops the A/D conversion.
No change, no effect on other bits.