Reset Operation - Fujitsu MB90390 Series Hardware Manual

7.4

Reset Operation

When a reset is cleared, the memory locations from which the mode data and the reset
vectors are read are selected according to the setting of the mode pins, and a mode
fetch is performed. Mode setting data determines the CPU operating mode and the
execution start address after a reset operation ends. For power-on or recovery from
stop mode by a reset, a mode fetch is performed when the oscillation stabilization wait
time elapses.
■ Overview of Reset Operation
Figure 7.4-1 shows the reset operation flow.
During a reset
Mode fetch
(Reset operation)
Normal operation
(Run state)
■ Mode Pins
Setting the mode pins (MD0 to MD2) specifies how to fetch the reset vector and the mode data. Fetching
the reset vector and the mode data is performed in the reset sequence. See Section "9.2 Mode Pins of
Memory Access Mode", for details on mode pins.
Figure 7.4-1 Reset Operation Flow
Power-on reset
Stop mode
Oscillation stabilization wait
and reset state
Fetching the mode data
Fetching the reset vector
CPU executes an instruction,
fetching instruction codes from
the address indicated by the
reset vector.
CHAPTER 7 RESETS
External reset
Software reset
Watchdog timer reset
Pin state and function
change associated with
external bus mode
131