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CHAPTER 19 UART0, UART1
19.9.1
Flag Set Timings for a Receive Operation
(Mode0, Mode1, Mode3)
The RDRF, ORFE, and PE flags are set and an interrupt request to the CPU generated
when the final stop bit is detected indicating the end of reception transfer. The data in
UIDR0, UIDR1 is invalid when either the ORFE or PE bit is active.
■ Flag Set Timings for a Receive Operation (in Mode0, Mode1, Mode3)
Figure 19.9-1 shows the RDRF set timing (mode0, mode1, mode3), Figure 19.9-2 shows the ORFE set
timing (mode0, mode1, mode3), and Figure 19.9-3 show the PE set timing (mode0, mode1, mode3).
Receive interrupt
Data
RDRF = 1
ORFE
Receive interrupt
Receive interrupt
330
Figure 19.9-1 RDRF Set Timing (Mode0, Mode1, Mode3)
Data
RDRF
Figure 19.9-2 ORFE Set Timing (Mode0, Mode1, Mode3)
Stop
(Overrun error)
Figure 19.9-3 PE Set Timing (Mode0, Mode1, Mode3)
Data
PE
Stop
(Stop)
Data
RDRF = 0
ORFE
Receive interrupt
(Stop)
Stop
Stop
(Framing error)
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