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23.6.1
Control Status Register (CSR)
The lower 8 bits with the CAN control status register (CSR) is prohibited from executing
any bit manipulation instructions (Read-Modify-Write (RMW) instructions).
Only in the case of HALT bits unchanged, use any bit manipulation instructions without
problems (initialization of the macro instructions, etc.).
■ Control Status Register (CSR) (Lower)
Figure 23.6-1 Configuration of the Control Status Register (Lower Byte)
Address:
CAN0: 003700
CAN1: 003900
CAN2: 003B00
CAN3: 003D00
CAN4: 003F00
R/W
:
Readable and writable
W
:
Write only
X
:
Undefined value
-
:
Undefined
:
Initial value
7
6
5
4
3
bit
-
-
-
-
H
H
H
R/W
-
-
-
-
R/W
H
H
CSR0/CSR1/CSR2/CSR3/CSR4 (lower)
2
1
0
Initial value
0 X X X X 0 X 1
W R/W
bit 0
HALT
Write: Cancels bus operation stop
0
Read: Bus operation not in stop mode
Write: Stops bus operation
1
Read: Bus operation in stop mode
bit 1
Reserved
0
Do not write "1" to this bit
bit 2
NIE
Node status transition interrupt enable bit
0
Node status transition interrupt enabled
1
Node status transition interrupt disabled
bit 7
TOE
0
General-purpose port pin
1
Transmit pin of CAN controller
CHAPTER 23 CAN CONTROLLER
B
Bus Operation stop bit
Reserved bit
Transmit output enable bit
467
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