Fujitsu MB90390 Series Hardware Manual page 140

CHAPTER 6 CLOCK MODULATOR
Table 6.3-1 Function of Each Bit of the Clock Modulator Control Register (3/3)
Bit name
FMOD:
Frequency
bit1
modulation
enable bit
PDX:
bit0
Power down bit
Figure 6.3-2 shows the status of the modulator.
112
"0": Frequency modulation disabled.
"1": Frequency modulation enabled.
Note: Do not set this bit to "1" with MB90F394H.
• To enable the modulator in frequency modulation mode, FMOD must be set to "1".
• Before the modulator can be enabled, the PLL must deliver a stable reference clock
(PLL lock time must be elapsed).
• The specified PLL frequency range for frequency modulation mode is 15 MHz to 25
MHz.
• Each PLL output frequency offers a set of possible modulation parameters. The
selected setting (CMPR register) and the PLL frequency must match.
Please refer to the CMPR register description.
• Whenever the PLL output frequency is changed or the PLL is switched OFF e.g. in
power down modes, the modulator must be disabled before → FMOD=0 and
FMODRUN=0.
• Before the modulator can be enabled, it must be switched from power down to active
mode by setting PDX to "1". And the startup time of 6 μs must be awaited.
Please refer to the application note for a description of the recommended startup
sequence.
• Before the modulator can be enabled in frequency modulation mode, a proper setting
must be selected via the parameter register CMPR.
• The modulator must not be set to frequency modulation and phase modulation mode
at the same time (FMOD=1, PDX=1 and PMOD=1). Before the modulator can be
enabled in frequency modulation mode (FMOD=1, PDX=1), the PMOD bit must be
set to "0".
• After enabling the frequency modulation mode by setting FMOD to "1", the
modulator is calibrated. During this time, the clock is unmodulated. Therefore the
output clock does not switch immediately to modulated clock. The status of the
clock (frequency modulated / unmodulated) is indicated by the FMODRUN status
bit. Please refer to the FMODRUN bit description.
• Due to the synchronization of the FMOD signal and the synchronized switching to
unmodulated clock, it takes less than 9 × T0 (input clock period) before the clock
switches to unmodulated clock after the modulator is disabled. The modulator can be
disabled at any time.
• Before changing the parameter register CMPR, the modulator must be disabled →
FMOD=0 and FMODRUN=0.
"0": Power down mode
"1": Power up
• PDX is the power down signal for the modulator. Before the frequency modulation
mode can be enabled, this bit must be set to "1" and the startup time of 6 μs must be
awaited. Please refer to the application note for a description of the recommended
startup sequence.
• For phase modulation mode (PMOD bit), the modulator must remain in power down
mode. I.e. PDX must be set to "0".
• Before switching to power down mode (PDX=0), the modulator must be disabled →
FMOD=0 and FMODRUN=0.
Function