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LIN bus timing
Figure 20.7-9 LIN Bus Timing and UART2, UART3 Signals
old serial clock
LIN
bus
(SIN2/SIN3)
RXE
LBD
(IRQ0)
LBIE
Internal
Signal
to ICU
IRQ from
ICU
RDRF
(IRQ0)
RIE
Read
RDR2/RDR3
by CPU
Reception Interrupt
enable
LIN break begins
LIN break detected and Interrupt
IRQ cleared by CPU (LBD -> 0)
LBIE disable
IRQ cleared: Begin of Input Capture
IRQ cleared: Calculate & set new baud rate
no clock used
(calibration frame)
ICU count
IRQ from ICU
IRQ from ICU
Reception enable
Edge of Start bit of Identifier byte
Byte read in RDR2/RDR3
CHAPTER 20 UART2, UART3
new (calibrated) serial clock
RDR2/RDR3 read by CPU
391
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