Fujitsu MB90390 Series Hardware Manual page 346

CHAPTER 19 UART0, UART1
■ Status Register (USR) Contents
Table 19.3-2 Function of Each Bit of the Status Register
Bit name
RDRF:
bit15 Receiver Data
Register full bit
ORFE:
bit14 Overrun/Framing
Error bit
PE:
bit13
Parity error bit
TDRE:
bit12 Transmission Data
Register empty bit
RIE:
bit11 Reception interrupt
enable bit
TIE:
bit10 Transmission
interrupt enable bit
RBF:
bit9 Receiver Busy Flag
bit
TBF:
bit8 Transmitter Busy
Flag bit
318
This flag indicates the state of the UIDR (input data register). The flag is set when the receive data is
loaded into UIDR. Reading UIDR or writing "0" to RFC in the UMC register clears the flag. If RIE
is active, a receive interrupt request is generated when RDRF is set.
"0": No data in UIDR
"1": Data present in UIDR
The flag is set when an overrun or framing error occurs in receiving. Writing "0" to RFC in the
UMC register clears the flag. When this flag is set, the data in UIDR is invalid and the load from the
receive shifter to UIDR is not performed. If RIE is active, a receive interrupt request is generated
when ORFE is set.
"0": No error
"1": Error (see table below)
RDRF ORFE
0 0
0 1
1 0
1 1
The flag is set when a receive parity error occurs. Writing "0" to RFC in the UMC register clears the
flag. When this flag is set, the data in UIDR is invalid and the load from the receive shifter to UIDR
is not performed. If RIE is active, a receive interrupt request is generated when PE is set.
"0": No parity error
"1": Parity error
This flag indicates the state of the UODR (output data register). Writing transmit data to the UODR
register clears the flag. The flag is set when the data is loaded to the transmit shifter and the
transmission is started. If TIE is active, a transmit interrupt request is generated when TDRE is set.
"0": Data present in UODR
"1": No data in UODR
Enables receive interrupt requests.
"0": Disable interrupts.
"1": Enable interrupts.
Enables transmit interrupt requests. A transmit interrupt is generated immediately if transmit
interrupts are enabled when TDRE is "1".
"0": Disable interrupts.
"1": Enable interrupts.
This flag indicates that UART0, UART1 is receiving input data. The flag is set when the start bit is
detected and cleared when the stop bit is detected.
"0": Receiver idle
"1": Receiver busy
This flag indicates that UART0, UART1 is transmitting input data. The flag is set when transmit
data is written to the UODR register and cleared when transmission completes.
"0": Transmitter idle
"1": Transmitter busy
Function
UIDR0, UIDR1 State
Empty
Framing error
Vaild data
Overrun error