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■ Bus Status Register (IBSR) Contents
Table 21.2-1 Function of Each Bit of the Bus Status Register (IBSR) (1/2)
Bit name
BB:
bit7
Bus busy bit
RSC:
bit6
Repeated start
condition bit
AL:
bit5
Arbitration loss
bit
LRB:
bit4
Last received bit
TRX:
bit3
Transferring data
bit
AAS:
bit2
Addressed as
slave bit
This bit indicates the status of the I
"0": Stop condition detected (bus idle)
"1": Start condition detected (bus in use)
This bit is set to "1" if a start condition is detected. It is reset upon a stop condition.
This bit indicates detection of a repeated start condition.
"0": Repeated start condition not detected.
"1": Start condition detected (bus in use).
This bit is cleared at the end of an address data transfer (ADT= 0) or detection of a stop
condition.
This bit indicates an arbitration loss.
"0": No arbitration loss detected.
"1": Arbitration loss occurred during master sending.
This bit is cleared by writing "0" to the INT bit or by writing "1" to the MSS bit in the IBCR
register.
An arbitration loss occurs if:
- the data sent does not match the data read on the SDA line at the rising SCL edge
- a repeated start condition is generated by another master in the first bit of a data byte
- the interface could not generate a start or stop condition because another slave pulled the
SCL line low before
This bit is used to store the acknowledge message from the receiving side.
"0": Receiver acknowledged.
"1": Receiver did not acknowledge.
It is changed by the hardware upon reception of bit9 (acknowledge bit) and is also cleared
by a start or stop condition.
This bit indicates data sending operation during data transfer.
"0": Not transmitting data.
"1": Transmitting data.
It is set to "1":
- if a start condition was generated in master mode
- at the end of a first byte transfer and read access as slave or sending data as master
It is set to "0" if:
- the bus is idle (BB= 0)
- an arbitration loss occurred
- a "1" is written to the SCC bit during master interrupt (MSS = 1 and INT = 1)
- the MSS bit being cleared during master interrupt (MSS = 1 and INT = 1)
- the interface is in slave mode and the last transferred byte was not acknowledged
- the interface is in slave mode and it is receiving data
- the interface is in master mode and is reading data from a slave
This bit indicates detection of a slave addressing.
"0": Not addressed as slave.
"1": Addressed as slave.
This bit is cleared by a (repeated-) start or stop condition. It is set if the interface detects its
seven and/or ten bit slave address.
CHAPTER 21 400 kHz I
Function
2
C bus.
2
C INTERFACE
411
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